BUFGThis design element is a high-fanout buffer that connects signals to the global routing resources for low-skew distribution of the signal. BUFGs are typically used on clock nets as well other high-fanout nets like sets, resets, and clock enable
BUFG全局时钟缓冲器，可以走专门的时钟资源，增强驱动能力，减少传播延迟
// BUFG: General Clock Buffer
// UltraScale
// Xilinx HDL Language Template, version 2024.1
BUFG BUFG_inst (
.O(O), // 1-bit output: Clock output.
.I(I) // 1-bit input: Clock input.
);
// End of BUFG_inst instantiation
BUFGCEThis design element is a general clock buffer with a single gated input. When clock enable (CE) is Low (inactive), its O output is 0. When CE is High, the I input is transferred to the O output.
带使能端口的BUFG
// BUFGCE: General Clock Buffer with Clock Enable
// UltraScale
// Xilinx HDL Language Template, version 2024.1
BUFGCE #(
.CE_TYPE("SYNC"), // ASYNC, HARDSYNC, SYNC
.IS_CE_INVERTED(1'b0), // Programmable inversion on CE
.IS_I_INVERTED(1'b0), // Programmable inversion on I
.SIM_DEVICE("ULTRASCALE_PLUS") // ULTRASCALE, ULTRASCALE_PLUS
)
BUFGCE_inst (
.O(O), // 1-bit output: Buffer
.CE(CE), // 1-bit input: Buffer enable
.I(I) // 1-bit input: Buffer
);
// End of BUFGCE_inst instantiation
BUFGCE_DIVBUFGCE_DIV is a general clock buffer with an enable and divide function
能够进行简单分频的BUFG，可进行1~8 分频
// BUFGCE_DIV: General Clock Buffer with Divide Function
// UltraScale
// Xilinx HDL Language Template, version 2024.1
BUFGCE_DIV #(
.BUFGCE_DIVIDE(1), // 1-8
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
.IS_CE_INVERTED(1'b0), // Optional inversion for CE
.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
.IS_I_INVERTED(1'b0), // Optional inversion for I
.SIM_DEVICE("ULTRASCALE_PLUS") // ULTRASCALE, ULTRASCALE_PLUS
)
BUFGCE_DIV_inst (
.O(O), // 1-bit output: Buffer
.CE(CE), // 1-bit input: Buffer enable
IBUFDSThe usage and rules corresponding to the differential primitives are similar to the single-ended SelectIO primitives. Differential SelectIO primitives have two pins to and from the device pads to show the P and N channel pins in a differential pair. N channel pins have a B suffix
输入差分信号转为单端信号
// IBUFDS: Differential Input Buffer
// UltraScale
// Xilinx HDL Language Template, version 2024.1
IBUFDS IBUFDS_inst (
.O(O), // 1-bit output: Buffer output
.I(I), // 1-bit input: Diff_p buffer input (connect directly to top-level port)
.IB(IB) // 1-bit input: Diff_n buffer input (connect directly to top-level port)
);
// End of IBUFDS_inst instantiation
OBUFDSThe OBUFDS is a differential output buffer primitive
单端信号转化为差分信号输出
// OBUFDS: Differential Output Buffer
// UltraScale
// Xilinx HDL Language Template, version 2024.1
OBUFDS OBUFDS_inst (
.O(O), // 1-bit output: Diff_p output (connect directly to top-level port)
.OB(OB), // 1-bit output: Diff_n output (connect directly to top-level port)
.I(I) // 1-bit input: Buffer input
);
// End of OBUFDS_inst instantiation
IBUFDS_GTE4/ OBUFDS_GTE4IBUFDS_GTE4 is the gigabit transceiver input pad buffer component. The REFCLK signal should be routed to the dedicated reference clock input pins on the serial transceiver, and the user design should instantiate the IBUFDS_GTE4 primitive in the user design. See the Transceivers User Guide for more information on PCB layout requirements, including reference clock requirements
专门给GT(SERDES)参考时钟的BUF，refclk差分、单端转化
// IBUFDS_GTE4: Gigabit Transceiver Buffer
// UltraScale
// Xilinx HDL Language Template, version 2024.1
IBUFDS_GTE4 #(
.REFCLK_EN_TX_PATH(1'b0), // Refer to Transceiver User Guide.
.REFCLK_HROW_CK_SEL(2'b00), // Refer to Transceiver User Guide.
.REFCLK_ICNTL_RX(2'b00) // Refer to Transceiver User Guide.
)
IBUFDS_GTE4_inst (
.O(O), // 1-bit output: Refer to Transceiver User Guide.
.ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide.
.CEB(CEB), // 1-bit input: Refer to Transceiver User Guide.
.I(I), // 1-bit input: Refer to Transceiver User Guide.
.IB(IB) // 1-bit input: Refer to Transceiver User Guide.
);
// End of IBUFDS_GTE4_inst instantiation